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Real Designs, Built by Real Students

Every Atharva Silicon program ends in a hands-on project — not a slide deck. Here's a sample of the work our students have shipped across each specialization.

RISC
Completed
LOGICAL DESIGN

8-Bit RISC Core

A synthesizable 8-bit RISC processor core built from the ground up in RTL, covering the fetch-decode-execute pipeline.

VerilogModelSimGTKWave
UVM
Completed
DESIGN VERIFICATION

SystemVerilog Testbench for a UART Module

A self-checking verification environment with constrained-random stimulus and functional coverage for a UART DUT.

SystemVerilogQuestaCoverage
PNR
Completed
PHYSICAL DESIGN

Full-Chip Place & Route on a Sample Netlist

Floorplanning through routing on a synthesized netlist, taken to a clean DRC/LVS-ready layout.

Cadence InnovusFloorplanningCTS
STA
Completed
PHYSICAL DESIGN

Timing Closure Report on a Multi-Clock Design

Setup/hold analysis and constraint debugging across clock domains, closing out every violating path.

PrimeTimeSDC ConstraintsMulti-Corner STA
OPAMP
Completed
LAYOUT DESIGN

Two-Stage Op-Amp Layout with Device Matching

Analog layout of a two-stage operational amplifier, applying matching techniques to minimize parasitic mismatch.

Cadence VirtuosoParasitic ExtractionDRC/LVS
ECO
Completed
LAYOUT DESIGN

Sign-Off Checklist Walkthrough on a Sample Block

A full run through ECO handling and pre-tape-out sign-off checks on a real design block.

ECO FlowSign-off ChecksCase Study
IOT
Completed
EMBEDDED DESIGN

Sensor-to-Cloud IoT Monitoring Node

A microcontroller-based sensor node reading temperature and humidity data, transmitted to a cloud dashboard.

Embedded CMicrocontroller Dev BoardUART/I2C
DBG
Completed
EMBEDDED DESIGN

Debug & Bring-Up of a Development Board Firmware

Bring-up, testing and debugging of firmware on a microcontroller board using simulation and hardware debug tools.

Embedded CDebugging ToolsSimulation Platform
FSM
Completed
LOGICAL DESIGN

UART/SPI Controller with FSM-Based Design

A finite-state-machine-driven communication controller, synthesized and verified against a reference testbench.

VerilogFSM DesignSynthesis

Build Your Own Portfolio Project

Every course track ends in a hands-on capstone like these — reviewed by a mentor before you add it to your portfolio.