ECO & Sign-off Checks
Course Description The ECO (Engineering Change Order) & Sign-off Checks module at Atharva Silicon Institute is designed to teach students the final and most critical stage of the VLSI Physical Design flow. This course focuses on implementing design changes late …
Course Description
The ECO (Engineering Change Order) & Sign-off Checks module at Atharva Silicon Institute is designed to teach students the final and most critical stage of the VLSI Physical Design flow. This course focuses on implementing design changes late in the design cycle and performing comprehensive sign-off verification to ensure the chip is ready for manufacturing.
Students will gain practical knowledge of how engineers fix timing violations, power issues, and design rule violations without affecting the overall layout. The course also covers industry-standard sign-off checks such as DRC, LVS, STA, IR drop, and EM analysis, which are essential before tape-out.
By the end of this module, learners will understand how to safely apply ECO changes, validate designs using sign-off tools, and ensure the chip meets all foundry requirements.
Tools Covered
Students will gain hands-on exposure to industry tools commonly used for ECO implementation and sign-off verification, including:
Synopsys Physical Design tools
Cadence Sign-off tools
Timing and verification analysis platforms
Who Should Enroll
Electronics & ECE students interested in VLSI Physical Design
Engineering graduates seeking semiconductor industry careers
Professionals looking to upgrade skills in chip design verification
Learners who want to understand tape-out and sign-off processes
Course Features
- Activities Physical Design
- Class Sizes 20
- Available Seats 10
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10 Students
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40 Hours
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5th Floor, opposite to the Prajay Megapolis partment, Gokul plots, KPHB, Hyderabad
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10 Students
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40 Hours
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10 Students
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40 Hours
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5th Floor, opposite to the Prajay Megapolis partment, Gokul plots, KPHB, Hyderabad