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Showing 1-4 of 4 results
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10 Students
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40 Hours
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5th Floor, opposite to the Prajay Megapolis partment, Gokul plots, KPHB, Hyderabad
Course Description The ECO (Engineering Change Order) & Sign-off Checks module at Atharva Silicon Institute is designed to teach students the final and most critical stage of the VLSI Physical...
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10 Students
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40 Hours
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5th Floor, opposite to the Prajay Megapolis partment, Gokul plots, KPHB, Hyderabad
Course Description Static Timing Analysis (STA) is one of the most critical stages in the VLSI physical design flow. It ensures that digital circuits operate reliably at the required clock...
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10 Students
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40 Hours
Course Description The CMOS Fundamentals & Layout course at Atharva Silicon Institute is designed to build a strong foundation in CMOS technology, digital circuit design, and IC layout techniques. This...
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10 Students
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40 Hours
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5th Floor, opposite to the Prajay Megapolis partment, Gokul plots, KPHB, Hyderabad
Course Description The Digital Physical Design Flow (Place and Route – PNR) course at Atharva Silicon Institute is designed to provide students and engineers with comprehensive knowledge of the complete...