Join the VLSI Physical Design Training Course in Hyderabad, at Atharva Silicon Institute and learn complete chip design flow including floorplanning, placement, CTS, routing, and STA. Gain industry-oriented skills with hands-on projects to start your career in the semiconductor industry.
Physical Design
The Physical Design (PD) course at Atharva Silicon is a comprehensive, industry-aligned training program designed to prepare students and professionals for real-world semiconductor design roles. From floorplanning to signoff, this course provides hands-on exposure to industry-standard tools, real project flows, and expert mentorship.
Whether you are a fresh graduate, working professional, or transitioning into VLSI, this course equips you with the skills and confidence to work on advanced ASIC and SoC designs.
- Industry-Oriented Curriculum – Designed by experts with real project experience.
- Hands-On Training – Work on live design blocks and complete end-to-end PD flow.
- Expert Faculty – Learn from experienced VLSI professionals.
- Placement Support – Resume building, mock interviews, and job assistance.
- Flexible Learning – Classroom, online, and hybrid training options.
- Lifetime Access – Course materials, recordings, and tool practice access.
- Understand the complete ASIC physical design flow.
- Perform floorplanning, placement, CTS, routing, and signoff.
- Analyze and fix timing, power, and signal integrity issues.
- Work with industry-standard EDA tools.
- Prepare for interviews and contribute to real silicon projects.
Introduction to VLSI Physical Design
- Overview of ASIC design flow
- Role of physical design in chip development
- Technology nodes and design challenges
Unix/Linux & Scripting Basics
- Linux commands for VLSI engineers
- Shell scripting fundamentals
- Introduction to Tcl for EDA tools
Floorplanning
- Die and core area estimation
- Aspect ratio and utilization
- IO planning and pin assignment
- Power planning and power grid design
- Macro placement strategies
Placement
- Standard cell placement
- Placement optimization techniques
- Congestion analysis and fixes
- Timing-driven placement
Clock Tree Synthesis (CTS)
- Clocking concepts and clock architecture
- Clock tree construction
- Skew, latency, and jitter optimization
- CTS strategies and best practices
Routing
- Global routing and detailed routing
- Routing constraints and DRC
- Signal integrity considerations
- Antenna effects and fixes
Static Timing Analysis (STA)
- Timing basics and constraints
- Setup, hold, and recovery/removal checks
- Multi-mode multi-corner (MMMC) analysis
- Timing closure strategies
Power, Signal Integrity & IR Analysis
- Power analysis (dynamic and leakage)
- IR drop analysis and fixes
- Electromigration (EM) analysis
- Crosstalk and noise analysis
- BE / BTech / ME / MTech students in ECE, EEE, or related fields
- Working professionals in VLSI, embedded, or electronics domains
- Engineers looking to switch careers into semiconductor design
- Fresh graduates aspiring for VLSI physical design roles
Students will gain hands-on experience with industry-standard EDA tools such as:
- Synopsys ICC2 / Fusion Compiler
- Cadence Innovus
- PrimeTime
- Calibre
- StarRC / Quantus
- Conceptual Learning – Strong foundation in theory.
- Hands-On Labs – Step-by-step practical sessions.
- Real-Time Projects – Work on complete PD flows.
- Assignments & Assessments – Regular evaluations to track progress.
- Interview Preparation – Technical questions, resume building, and mock interviews.
- Duration: 6 to 8 months (depending on batch format)
- Mode: Classroom / Online / Hybrid
- Session Type: Live instructor-led sessions with recordings
- Physical Design Engineer
- ASIC Engineer
- STA Engineer
- Layout Engineer
- CAD Engineer
- SoC Physical Design Engineer
- Industry-recognized certification
- Real project experience
- Lifetime access to course materials
- Dedicated placement assistance
- Networking with industry professionals